1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device to which data can be rewritten electrically.
2. Description of the Related Art
An EEPROM (Electrically Erasable Programable Read Only Memory) is well known as a ROM by which data once stored can be erased and further new data can be rewritten electrically. In this EEPROM, since no ultraviolet rays are required to erase stored data, being different from an EPROM, it is possible to erase and rewrite data electrically under the condition that the memory device is kept mounted on a board, so that this memory device is easy to use as various controlling apparatuses or as memory cards.
Recently, in particular, an EEPROM of NAND cell structure type has been developed as the EEPROM suitable for a larger capacity. In more detail, the EEPROM of NAND structure is provided with the following features: data writing and erasing operation can be realized on the basis of the tunnel effect, without injecting hot electrons, being different from the conventional memory cells of NOR cell type structure. Accordingly, the current passing through the memory cells is small and thereby the data can be rewritten in the unit of page. In other words, since a large quantity of data are erasable and rewritable, the memory device is usable as not only a memory cards but also is replaceable with a hard disk.
FIG. 1 shows two memory cell groups MCG of NAND structure each provided with 8 floating gates. In data read operation, the select gate (the word line WL (S)) of selected memory cells MC (1) and MC (2) are set to a low level ( referred to as "L" level, hereinafter ) and the select gates (the word lines WL (NS)) of the remaining 7 memory cells in the NAND cell groups are set to a high level (referred to as "H" level, hereinafter). Further, the gates (the select line SGD) of the select transistors T1 and the gates (the select line SGS) of the select transistors T2 are set to "H" level, respectively.
FIG. 2 shows a typical distribution of the threshold voltage of the non-volatile semiconductor memory device of NAND structure. In FIG. 2, the threshold voltages of the memory cells in which "0" data are written distribute on the positive side and further the threshold voltage of the "0" data cells is set to a value lower than the gate voltage ("H") of the non-selected transistors of the NAND cell groups. Therefore, when the threshold voltage of the selected memory cell MC (1) is positive (i.e., a data "0" is written), no current flows between the bit line BL (1) and the ground GND, so that the bit line BL (1) is set to "H" level. Further, when the threshold voltage of the selected memory cell MC (2) is negative (i.e., a data "1" is written), current flows between the bit line BL (2) and the ground GND, so that the bit line BL (2) is set to "L" level. Therefore, it is possible to read the data "0" or "1" of the memory cells MC (1) or MC (2) by sensing the voltage potentials of the bit lines BL (1) and BL (2) with a sense amplifier circuit.
The writing operation will be described hereinbelow with reference to FIG. 3. In the drawing, a high voltage (Vpp) of about 20 V is supplied to the select gate WL (S) of the selected memory cells from a row decoder. Further, an intermediate potential (VPI) of about 10 V is supplied to the select gates WL (NS) of the other remaining 7 non-selected memory cells. Under these conditions, the gate voltage (SGD) of the select transistors T1 is set to 12 V and the gate voltage of the select transistors T2 between the NAND cell group MCG and the source line is set to 0 V. Further, although not shown, 0 V is supplied to the select gates of the other NAND cell group. Under these conditions, when the bit line BL (1) is set to 0 V, the voltage potential difference between the select gate WL (S) of the selected memory cell MC (1) and the channel is set to 20 V, so that electrons are injected from the substrate to the floating gate only at the selected memory cell MC (1). At this time, in the other 7 memory cells of the same NAND cell group MCG (1), the voltage potential difference between the select gate and the channel is 10 V, so that electrons are not injected to the floating gates thereof. Further, when electrons are not injected to the selected memory cell MC (2); that is, "1" is required to be written, the voltage of VDPI (10 V) is supplied to the bit line BL (2). Under these conditions, electrons are not injected. In other words, it is possible to selectively write a data of "0" or "1", selectively.
The erasing operation will be described hereinbelow with reference to FIG. 4. In the erasing operation, the substrate is set to Vpp (about 20 V) and the select gate is set to 0 V, respectively. Under these conditions, electrons at the floating gate are extracted toward the substrate, so that a data is erased. In this case, the select lines SGD and SGS are set to Vpp (20 V) in order to reduce the gate stress at the select gates.
As described above, in the EEPROM of NAND structure, a data is written in dependence upon tunnel current. Accordingly, current flowing through the memory cells is extremely small in data writing operation, so that it is possible to write data to a great number (several hundreds to several thousands) of memory cells at the same time.
The data write and erasure sequences of the EEPROM of NAND type will be described with reference to FIGS. 5 and 6.
In the data write operation as shown in FIG. 5, first a data input command "80H" is inputted (in step S1) and further data to be written for one page are inputted (in step S2). The data are written until all the column addresses end (in steps S2 and S3). Here, a program command "10H" is inputted (in step S4). In this status, the chip is set to an automatic program mode. That is, control executes the program for writing a data (in step S5) and verifies the executed program; that is, the written data (in step S6). Whenever the program is executed normally and further verified, the number k of executed programs is incremented (in step S7) and further the incremented number k of programs is compared with a predetermined number n (in step S8). The above-mentioned procedure is repeated until all the bits are written properly. The number n of the repetitions is previously determined. On the basis of this repetition number, the chip is discriminated as being acceptable or not (non-defective or defective). In the data writing operation, a signal BUSY is outputted from a READY / BUSY terminal so that the writing operation can be known from the outside. After the data write operation ends normally, a flag read command "70H" is inputted (in step S9). Then, control reads the verified results stored in the internal register, and outputs the read verified results through an I/O terminal (in step S10). If the flag can be read (pass), the chip is discriminated as a non-defective product (in step S11). If cannot be read (fail), the chip is discriminated as a defective product (in step S12).
In the data erasing operation in FIG. 6, first an erase block input command "60H" is inputted (in step S1) and further erase block addresses are inputted (in step S2). Here, an erase command "DOH" is inputted (in step S3). In this status, the chip is set to an automatic erase mode. That is, control executes the erasing operation (in step S4) and verifies the executed erasing operation (in step S5). Whenever the erasing operation is executed and further verified, the number l of erasing operations is incremented (in step S6) and further the incremented number l of erasing operations is compared with a predetermined number n (in step S7). The number n of the repetitions is previously determined. On the basis of this repetition number, the chip is discriminated as being acceptable or not. In the data erasing operation, a signal BUSY is outputted from the READY / BUSY terminal so that the erasing operation can be known from the outside. After the erasing operation ends normally, a flag read command "70H" is inputted (in step S8). Then, control reads the verified results stored in the internal register, and outputs the read results through the I/O terminal (in step S10). If the flag can be read (pass), the chip is discriminated as a non-defective product (in step S11). If cannot be read (fail), the chip is discriminated as a defective product (in step S12).
In general, the characteristics of the EEPROM deteriorate markedly due to the deterioration of the oxide films, after the writing and erasing operation has been executed repeatedly. FIG. 7 shows an example of the data write and erase characteristics. This graph indicates that the time required for the memory cell to reach a predetermined threshold voltage increases with increasing number of data writing programs and data erasures (data rewriting times). Therefore, it is not preferable from the reliability standpoint to use the chip in which the above-mentioned time to the threshold voltage begins to increase beyond a usable limit.
In this case, however, there exists a problem in that it is difficult to discriminate the beginning of the deterioration in the chip characteristics (the time point at which the time required to reach the threshold voltage begins to increase) as far as the data are written and erased in the automatic mode.
Further, in the conventional memory devices, the limitation in the number of the data writing and erasing operations is fixedly determined (e.g., 100 times) with the use of a mask, irrespective the ship samples. However, since the data writing and erasing characteristics usually differ according to the production lot, there exists a problem in that the above-mention operation margin (the allowable write and erasing operation limit) differs according to the chip samples.
In other words, in the conventional non-volatile semiconductor memory device, when data are written and erased repeatedly in the automatic mode, it has been impossible to know the chip deterioration conditions from the outside.
Further, since the number of times for data writing and erasing operations is fixedly determined by use of a mask during the chip manufacturing process, irrespective of the chip samples of different lots, there exists a problem in that the operation margin to the above-mentioned number of usable times differs according to the chip samples.